lom>showboards -p v
Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.3 Build_03
/N0/IB6 Yes 5.20.3 Build_03
/N0/SB0 Yes 5.20.13 Build_01
/N0/SB2 Yes 5.20.3 Build_03
/N0/SB4 Yes 5.20.6 Build_02
lom>showsc -v
SC: SSC1
System Controller V2
SC date: Fri Jan 15 02:16:00 PST 2008
PST GMT-08:00 Pacific Standard Time
SC uptime: 6 minutes 26 seconds
ScApp version: 5.20.3 Build_03
Version build: 3.0
Version String: 5.20.3
RTOS version: 46
SC POST diag level: max
Clock source is: 75MHz
Solaris Host Status: Powered Off
Chassis HostID: 845xxxxx
PROC RTUs installed: 0
PROC Headroom Quantity: 0
lom>
lom>showboards -p version -v
Component Segment Compatible In Date Time Build Version
--------- ------- ---------- -- ---- ---- ----- -------
SSC1/FP0 - - - - - - RTOS version: 46
SSC1/FP1 ScApp Reference 12 10/21/2006 06:38 3.0 5.20.3
SSC1/FP1 Ver - - 10/21/2006 06:38 3.0 5.20.3 Build_03
/N0/IB6/FP0 iPOST Yes 12 10/21/2006 06:36 3.0 5.20.3
/N0/IB6/FP0 Ver - - 10/21/2006 06:38 3.0 5.20.3 Build_03
/N0/IB6/FP0 Info - 12 10/21/2006 06:38 3.0 5.20.3
/N0/SB0/FP0 POST Yes 12 06/04/2009 02:44 1.0 5.20.13
/N0/SB0/FP0 OBP Yes 12 06/04/2009 02:43 1.0 5.20.13
/N0/SB0/FP0 Ver - - 06/04/2009 02:46 1.0 5.20.13 Build_01
/N0/SB0/FP0 Info - 12 06/04/2009 02:46 1.0 5.20.13
/N0/SB0/FP1 POST Yes 12 06/04/2009 02:44 1.0 5.20.13
/N0/SB0/FP1 OBP Yes 12 06/04/2009 02:43 1.0 5.20.13
/N0/SB0/FP1 Ver - - 06/04/2009 02:46 1.0 5.20.13 Build_01
/N0/SB0/FP1 Info - 12 06/04/2009 02:46 1.0 5.20.13
/N0/SB2/FP0 POST Yes 12 10/21/2006 06:25 3.0 5.20.3
/N0/SB2/FP0 OBP Yes 12 10/21/2006 06:21 3.0 5.20.3
/N0/SB2/FP0 Ver - - 10/21/2006 06:29 3.0 5.20.3 Build_03
/N0/SB2/FP0 Info - 12 10/21/2006 06:29 3.0 5.20.3
/N0/SB2/FP1 POST Yes 12 10/21/2006 06:25 3.0 5.20.3
/N0/SB2/FP1 OBP Yes 12 10/21/2006 06:21 3.0 5.20.3
/N0/SB2/FP1 Ver - - 10/21/2006 06:29 3.0 5.20.3 Build_03
/N0/SB2/FP1 Info - 12 10/21/2006 06:29 3.0 5.20.3
/N0/SB4/FP0 POST Yes 12 05/23/2007 08:56 2.0 5.20.6
/N0/SB4/FP0 OBP Yes 12 05/23/2007 08:54 2.0 5.20.6
/N0/SB4/FP0 Ver - - 05/23/2007 08:57 2.0 5.20.6 Build_02
/N0/SB4/FP0 Info - 12 05/23/2007 08:57 2.0 5.20.6
/N0/SB4/FP1 POST Yes 12 05/23/2007 08:56 2.0 5.20.6
/N0/SB4/FP1 OBP Yes 12 05/23/2007 08:54 2.0 5.20.6
/N0/SB4/FP1 Ver - - 05/23/2007 08:57 2.0 5.20.6 Build_02
/N0/SB4/FP1 Info - 12 05/23/2007 08:57 2.0 5.20.6
Based on this information, SB0 have version 5.20.13, SB2 have version 5.20.3 and SB4 have 5.20.6 firmware version. RTOS has firmware version 5.20.3 as well, then we will upgrade all the components into versions 5.20.14. Below are step by step :
1. Download Patch 114527-15
2. Save the file on an internal server (the server that is still a network with the server firmware to be upgraded.
3. flashupdate -f ftp://root:jadulbanget@192.168.12.101///tmp/114527-15/114527-15 scapp rtos
As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.
Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.
Do you want to continue? [no] yes
Waiting for critical processes to finish. This may take a while.
Critical processes have finished.
No boards can be updated.
Rebooting the SC to automatically complete the upgrade.
Rebooting. All network client connections closed. Reestablish any needed connections.
Fri Jan 15 02:21:21 app1lom lom: Stopping all services on this SC
Fri Jan 15 02:21:21 app1lom lom: All services on this SC have been stopped.
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 46 2006/09/26 07:52
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 128MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2
COM4 port _ Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002229
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.0 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.50 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 29.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up
Flashupdate
Verifying network connectivity to 192.168.12.101... Passed.
Connecting to 192.168.12.101...
Transferring sgrtos.flash via FTP : 2048 Transferring sgrtos.flash via FTP : 4608
-------- truncated -------
Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 0/11 = 100%
ok
Connecting to 192.168.12.101...
Transferring sgsc.flash via FTP : 2048 Transferring sgsc.flash via FTP : 4608
------------truncated file ------------
Transferring sgsc.flash via FTP : 6553876
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 0/101 = 0%
----------- truncated -----------
Updating flashprom sectors at address 0x36000000: 101/101 = 100%
ok
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 128MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2
COM4 port _ Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002229
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.50 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 30.0 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up
Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Sun Fire System Firmware
RTOS version: 49
ScApp version: 5.20.14 Build_02
SC POST diag level: min
The date is Monday, January 14, 2008, 2:29:55 AM PST.
Fri Jan 15 02:29:57 mylom lom: Boot: ScApp 5.20.14, RTOS 49
Fri Jan 15 02:30:02 mylom lom: Updating config data from the SCC
Fri Jan 15 02:30:04 mylom lom: Caching ID information
Fri Jan 15 02:30:05 mylom lom: Clock Source: 75MHz
Fri Jan 15 02:30:10 mylom lom: /N0/PS0: Status is OK
Fri Jan 15 02:30:11 mylom lom: /N0/PS1: Status is OK
Fri Jan 15 02:30:11 mylom lom: /N0/PS2: Status is OK
Fri Jan 15 02:30:12 mylom lom: /N0/PS3: Status is OK
Fri Jan 15 02:30:12 mylom lom: Chassis is in single partition mode.
Fri Jan 15 02:31:13 mylom lom: /N0/FT0, fan speed, High (4,2)
Fri Jan 15 02:32:32 mylom lom: Starting telnet server ...
Enter Password:
Connected.
lom>
4. Verify output
lom>showsc
SC: SSC1
System Controller V2
SC date: Fri Jan 14 02:33:10 PST 2008
SC uptime: 3 minutes 22 seconds
ScApp version: 5.20.14 Build_02
RTOS version: 49
Solaris Host Status: Powered Off
Chassis HostID: 845xxxx
PROC RTUs installed: 0
PROC Headroom Quantity: 0
lom>showboards -p v
Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.14 Build_02
/N0/IB6 Yes 5.20.3 Build_03
/N0/SB0 Yes 5.20.13 Build_01
/N0/SB2 Yes 5.20.3 Build_03
/N0/SB4 Yes 5.20.6 Build_02
5. Upgrade Component SB and IB
lom>flashupdate -f ftp://root:jadulbanget@192.168.12.101///tmp/114527-15/114527-15 all rtos
As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.
After this update you must reboot each active domain that was upgraded.
Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.
Do you want to continue? [no] y
Waiting for critical processes to finish. This may take a while.
Critical processes have finished.
Retrieving: flashupdate -f ftp://root:jadulbanget@192.168.12.101///tmp/114527-15/114527-15/lw8cpu.flash
Validating ................... Done
Programming PROM /N0/SB0/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB0/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB2/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB2/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB4/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB4/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Retrieving: flashupdate -f ftp://root:jadulbanget@192.168.12.101///tmp/114527-15/114527-15/lw8pci.flash
Validating ........ Done
Programming PROM /N0/IB6/FP0
Erasing ....... Done
Programming ....... Done
Verifying ....... Done
Rebooting the SC to automatically complete the upgrade.
Rebooting. All network client connections closed. Reestablish any needed connections.
Fri Jan 15 02:40:15 app1lom lom: Stopping all services on this SC
Fri Jan 15 02:40:15 app1lom lom: All services on this SC have been stopped.
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 128MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2
COM4 port _ Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002228
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 25.0 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.50 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 31.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up
Flashupdate
Verifying network connectivity to 192.168.12.101... Passed.
Connecting to 192.168.12.101...
Transferring sgrtos.flash via FTP : 2048
---- Truncated -----
Transferring sgrtos.flash via FTP : 696120
Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 0/11 = 0%Updating flashprom sectors at address 0x20000000: 11/11 = 100%
ok
Connecting to 192.168.12.101...
Transferring sgsc.flash via FTP : 2048
------------truncated --------------
Transferring sgsc.flash via FTP : 6553876
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 0/101 = 0%Updating flashprom sectors at address 0x36000000: 9/101 = 8%Updating flashprom sectors at address 0x36000000: 40/101 = 39%Updating flashprom sectors at address 0x36000000: 65/101 = 64%Updating flashprom sectors at address 0x36000000: 89/101 = 88%Updating flashprom sectors at address 0x36000000: 101/101 = 100%
ok
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 49 2009/08/28 05:26
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 128MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
MemBankAddrTest: start address = 0x04000000
MemBankAddrTest: start address = 0x08000000
MemBankAddrTest: start address = 0x0c000000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port _ Intr #2
COM4 port _ Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x00000000
REF : 0x00002228
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 0.0 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009B) :1.51
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 25.0 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 23.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 31.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
Using SCC MAC address
MAC address is 0:13:4e:5a:2a:6f
Hostname: mylom
Address: 192.168.22.10
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 192.168.22.1
interrupt: 100 Mbps full duplex link up
Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Sun Fire System Firmware
RTOS version: 49
ScApp version: 5.20.14 Build_02
SC POST diag level: min
The date is Friday, January 14, 2008, 2:46:47 AM PST.
Fri Jan 15 02:46:49 mylom lom: Boot: ScApp 5.20.14, RTOS 49
Fri Jan 15 02:46:56 mylom lom: Caching ID information
Fri Jan 15 02:46:58 mylom lom: Clock Source: 75MHz
Fri Jan 15 02:47:02 mylom lom: /N0/PS0: Status is OK
Fri Jan 15 02:47:03 mylom lom: /N0/PS1: Status is OK
Fri Jan 15 02:47:03 mylom lom: /N0/PS2: Status is OK
Fri Jan 15 02:47:04 mylom lom: /N0/PS3: Status is OK
Fri Jan 15 02:47:04 mylom lom: Chassis is in single partition mode.
Fri Jan 15 02:49:30 mylom lom: Starting telnet server ...
Enter Password:
Connected.
lom>
6. Verify output
lom>showboards -p v
Component Compatible Version
--------- ---------- -------
SSC1 Reference 5.20.14 Build_02
/N0/IB6 Yes 5.20.14 Build_02
/N0/SB0 Yes 5.20.14 Build_02
/N0/SB2 Yes 5.20.14 Build_02
/N0/SB4 Yes 5.20.14 Build_02
0 komentar:
Post a Comment